Vitis Unified Software Platform 2022.2 Latest Update

This article was written by Product Marketing Manager, AMD Xilinx Vitis Unified Software Platform

Written by Eddie Wu

Vitis™ Unified Software Platform Version 2022.2 has been officially released! Major enhancements include the following:

Provides new Vitis library capabilities for Versal AI Engine arrays:

DSP Library - Enhanced Features.

Solver library functions.

Vision library function.

Ultrasound library function.

Design flow enhancements for Versal devices:

Control the relative placement of cores in the AI ​​engine array to improve performance and utilization.

Enhanced configuration and debug capabilities for Versal® ACAP designs, including deadlock detection, larger routing data acquisition, RTL/Python testbench support.

New simulation options for heterogeneous designs within the Vitis integrated design environment.

Below is a description of some of the major enhancements:

The Vitis library has been enhanced to support more AI engine array capabilities

The DSP library now supports very high sample rate (SSR) FIR filters through coefficient reloading and dynamic point size. Added FFT windowing element to the FFT function pointing to the AI ​​engine array.

For the solver library, two new matrix factorization functions have been added to the AI ​​engine array, QR factorization and Cholesky factorization. These two are widely used matrix operations.

The Vitis vision library adds four new capabilities to the AI ​​engine array: Global Tone Mapping (GTM), Color Correction Matrix, 3D Lookup Table, and V4L2 compliant dynamic reconfiguration.

Version 2022.2 also offers new ultrasound libraries, including L1 to L3 functions:

The L1 routine provides Basic Linear Algebra Subroutine (BLAS)-like functionality for ultrasound.

L2 routines provide AI engine graphs for functions such as focusing, apodization, and b-splines.

The L3 routines provide ultrasound subsystems such as synthetic aperture, plane wave, and scanline beamforming.

See below for a more detailed description of the Vitis library provided to the AI ​​engine in versions 2022.1 and 2022.2.

Versal ACAP Design Process Enhancements

AI Engine Compiler

In this new release, AI Engine Relative Constraints provide a way to control the relative placement of cores within the AI ​​Engine. This is beneficial for users to obtain higher performance and fuller utilization from the AI ​​engine array. Constraints can be defined in Adaptive Data Flow (ADF) graph format and Java Object Notation (JSON) format.

ADF and JSON graph syntax examples are as follows:

What's New in Vitis Tools Simulation and Analysis

1. Use the Vitis Analyzer to configure, debug, and analyze the AI ​​engine

In version 2022.2, the state of the AI ​​engine can be analyzed during the hardware simulation phase in the Vitis analyzer to aid in debugging. Prior to version 2022.2, users had to build designs in hardware to perform the same analysis. This feature allows users to configure before building hardware, speeding up iterations while helping to shorten design cycles.

As of version 2022.1, deadlock detection can be enabled via xbutil and XRT on Linux. The same feature is now supported using the Xilinx System Debugger (XSDB). This is helpful for bare metal users. Can generate JSON files equivalent to those generated by xbutil. This file can be imported into the Vitis analyzer for viewing.

The deadlock detection process is as follows:

This new feature extends support for XRT to support XSDB processes based on AI engines.

2. Support software simulation with PS application on x86 host

In addition to QEMU on embedded platforms, users can now emulate software by compiling and running Processing System (PS) applications on an x86 emulator, speeding up software emulation. This feature eliminates the need to create an SD card image and boot Linux in QEMU, avoiding the associated overhead and speeding up turnaround time. Users can use XRT to control the acceleration core while they focus on the high-level functional model. Before using this feature, the Xilinx Runtime Library (XRT) must be installed on the host.

3. In addition to RTL, hardware simulation can also be performed using the SystemC functional model

Compared to RTL, the SystemC functional model enables faster compilation and shorter execution time. In addition, users can also use the C kernel and RTL kernel together to debug RTL blocks. In version 2022.2, C/C++ kernels, AXI4-Memory Map-based kernels, and AXI4-Stream-based kernels are supported.

New simulation options further enrich the functional simulation flow available to users, as shown below. These new simulation flows are primarily intended to assist in fast functional simulation.

4. Use a simple RTL testbench or a Python script-based traffic generator to provide support for the simulated AI engine core

This feature allows users to reuse the RTL testbench as a traffic generator (TG) or create a traffic generator using Python. Doing so allows the kernel to be individually verified without the need for a full platform.

The RTL simulator uses the above test platform, and x86SIM/AIESIM is responsible for simulating the C or AI engine kernel code, using Unix sockets and XTLM IPC interface to establish communication between the two processes, as follows:

With Vitis software platform version 2022.2, we now support Python, VHDL, Verilog and SystemVerilog based traffic generators.

More details

Please click "Read the full text" to download Vitis unified software platform version 2022.2 to learn more about the latest features and new functions.